The present invention relates to a semiconductor memory device, more particularly, to a delay locked loop of a semiconductor memory device.
A semiconductor memory device is an apparatus for storing data. When a data processing device such as a central processing unit (CPU) requests data, a semiconductor memory device outputs data stored where an address input from the data processing device indicates. On the other hand, a semiconductor memory device stores data supplied from a data processing device where an address input from the data processing device indicates.
As a system including a plurality of semiconductor memory devices needs to operate at higher speed, semiconductor memory devices are also required to output or store data at higher speed. It has been achieved by development of technology in reference to a semiconductor integrated circuit. In order to input/output a data at high speed, a synchronous memory device which is able to input/output data synchronized with a system clock was developed. Furthermore, a double data rate (DDR) synchronous memory device which is able to input/output a data at rising and falling edges of a system clock was developed in order to more increase an input/output speed of data.
Because inputting or outputting data at rising and falling edges of the system clock, the DDR synchronous memory device processes data twice during one period of the system clock. Particularly, the DDR synchronous memory device should output data whose output timing is accurately synchronized with a rising or a falling edge of the system clock. The DDR synchronous memory device includes a data output circuit for outputting a data synchronized with a rising or a falling edge of the system clock.
However, a system clock input into a semiconductor memory device is inevitably delayed by internal devices of the semiconductor memory device such as a clock input buffer and a transmitting line and transmitted to a data output circuit. Accordingly, if the data output circuit synchronizes a data with the delayed clock, an external device for receiving the data from the semiconductor memory device becomes to process an asynchronous data with a rising or falling edge of the system clock.
A semiconductor memory device is provided with a delay locked loop (DLL) for locking a delay of a system clock input to the semiconductor memory device, in order to solve above problem. The DDL is a circuit for compensating a delay time of the system clock. The delay time is time taken for the system clock to be transmitted to a data output circuit after input into the semiconductor memory device. The DLL finds how long it takes for the system clock to be delayed by the clock input buffer and the transmitting line. The DLL delays the system clock by a delay time corresponding to finding and outputs a delayed system clock to the data output circuit. That is, the system clock input to the semiconductor memory device, whose delay time is constantly locked by the DLL, is transmitted to the data output circuit. The data output circuit outputs data synchronized with a delay locked system clock. An external device accepts the data as accurately synchronized with the system clock input into the semiconductor memory device.
At a real operation, the delay locked system clock output from the DLL is transmitted to an output buffer at the time of a clock earlier than an output timing of data. And then, the data is outputted in synchronization with the delay locked system clock. Accordingly, the external device receives the data accurately in synchronization with a rising or a falling edge of the system clock input into the semiconductor memory device. The DLL is a device for finding how much earlier a data is outputted, in order to compensate the delay of the system clock input into the semiconductor memory device.
FIG. 1 is a signal timing diagram illustrating an operation of a conventional delay locked loop (DLL).
A DLL outputs a delay locked clock signal DLL_OUT being enabled earlier than an input clock signal CLKI by a predetermined time. A semiconductor memory device synchronizes data D0, D1 and D2 with the delay locked clock signal DLL_OUT and outputs them. When the semiconductor memory device outputs the data D0, D1 and D2 as above, an external device receives the data D0, D1 and D2 synchronized with a system clock signal CLK0.
Meanwhile, as a clock signal is inputted into the semiconductor memory device with a higher frequency, an operation margin necessary for the synchronous memory device to input or output a data at rising and falling edges of the clock signal decreases. Accordingly, it becomes more important for the semiconductor memory device to correct a duty cycle rate of the delay locked clock signal outputted from the DLL. The reason is because the operation margin for a semiconductor memory device to process data can be secured maximally when the duty cycle rate of the delay locked clock signal is in the proportion of 50 and 50. A DLL recently provided to a semiconductor memory device includes a circuit for correcting a duty cycle rate of an input clock signal.
However, it becomes more difficult for the DLL to output delay locked clock signal having a corrected duty cycle rate in spite of variation of an operation temperature, a supply voltage and a manufacture condition, because of an increase of a clock signal frequency. Unless the delay locked clock signal has the corrected duty cycle rate, an operation margin is insufficient at one of the rising and falling edges of the clock signal. The semiconductor memory device is not able to process data at a predetermined time.